
C8051T610/1/2/3/4/5/6/7
Port
P0
P1
P2
Pin Number 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Special
Function
Signals
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
T0
T1
Pin Skip 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x
x x x
Settings
P0SKIP
P1SKIP
P2SKIP
In this example, the crossbar is configured to assign the UART TX0 and RX0 signals, the
SMBus signals, and the SYSCLK signal. Note that the SMBus signals are assigned as a
pair, and there are no pins skipped using the XBR0 register.
These boxes represent the port pins which are used by the peripherals in this
configuration.
1 st TX0 is assigned to P0.4
2 nd RX0 is assigned to P0.5
3 rd SDA and SCL are assigned to P0.0 and P0.1, respectively.
4 th SYSCLK is assigned to P0.2
All unassigned pins can be used as GPIO or for other non-crossbar functions.
Figure 21.4. Priority Crossbar Decoder Example 1 - No Skipped Pins
Rev 1.1
119